The present invention, in various embodiments, relates generally to the field of semiconductor devices and more particularly, to programming of non-volatile memories.
A non-volatile or Flash memory device is a type of electrically erasable programmable read-only memory (EEPROM) and is used for non-volatile storage of data. Flash memory is being increasingly used to store execution codes and data in portable electronic products, such as computer systems, cameras, cellular telephones and other devices requiring non-volatile memory.
A conventional Flash memory comprises a memory array having rows and columns of memory cells. Each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding a charge and is separated by a thin oxide layer from source and drain regions contained in a substrate. Each of the memory cells can be electrically programmed (charged) by injecting electrons from the drain region through the oxide layer onto the floating gate. The charge can be removed from the floating gate by tunneling the electrons to the source through the oxide layer during an erase operation. Thus, the data in a memory cell is determined by the presence or absence of a charge on the floating gate.
Conventionally, the control gate of each memory cell of a row of the array is connected to a line (called a word-line) having a common voltage (word-line voltage), and the drain region of each memory cell of a column of the array is connected to a line (called a bit-line) having a common voltage (bit-line voltage). Flash memories currently have a typical operating voltage (Vcc) in the range of about 1.3 to 5 volts. A high voltage (or programming voltage), however, is usually required for programming and erase operations in a Flash memory. This high voltage is often 8 volts or higher. During a programming operation, electrons may be injected onto the floating gate by applying the high voltage to the control gate, e.g., via the word-line, with the bit-line being set to about Vcc-threshold voltage (Vt) for memory cells that are to be programmed to logic “0” and the bit-line being set to ground for memory cells that are to be programmed to logic “1.”
It is known that, during the programming of a row of the array, not all memory cells will accept or retain the initial programming. To determine if the memory cells in the row were properly programmed, a verify process reads the cells and compares the read values from the memory cells with the expected or originally programmed values. If one or more memory cells have not been properly programmed, the programming and verify steps are iteratively performed with the programming voltages incrementally increased.
While Flash memories provide various advantages over other memory technologies, the successive program and verify cycles results in an undesirably lengthy programming process for storing data. Accordingly, there is a need for a method and system for reducing the overall programming latency associated with Flash memory arrays.